New requirements for the MAC (medium-access control) and PHY (physical-layer interface) of a wireless-communications system can pose significant challenges for system designers looking to quickly get ...

Jena -- March 19 2009 - MAZeT GmbH offers IP cores for the Interbus protocol (SUPI4 / Phoenix Contact) for implementation in FPGAs and ASICs. The protocol chip for serial communication interfaces in ...

With the advent of new high-bandwidth wireless data technologies such as 802.11b (Wi-Fi, WLAN), design efforts based on legacy chipset architectures have become a formidable problem. Providing the ...

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leader in ASIC design services and IP solutions, announces joining the Intel Foundry Accelerator Design Services, ...

Integrated flow proven to deliver better timing, area and turnaround time for structured ASIC designs SANTA CLARA, Calif., July 21, 2006 ––Magma® Design Automation Inc. (Nasdaq: LAVA), a provider ...

SOPHIA-ANTIPOLIS, France--(BUSINESS WIRE)--Menta S.A.S., a premier supplier of embedded FPGA (eFPGA) solutions, today announced the industry’s first eFPGA soft IP offering, giving engineers greater ...

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...

With the complexity explosion occurring in SoC design today, there is a relentless force to push design decisions further up in terms of abstraction. Resolving issues at the gate level is not possible ...

It’s a changing world. In 1851, the headline of an editorial in an Indiana newspaper urged readers to “Go West, Young Man!” Fast forward 150 years, and you ...

In 1988 SILVAR-LISCO signed a multi-year, multi-million-dollar contract with Philips for the development of a DSP-specific ASIC design flow. The design environment for DSP ASIC implementation was ...