EDN

Accelerate DSP algorithms with IP blocks

Elixent's DFA1000 IP (intellectual-property) block can accelerate the execution of DSP code in designs of SOC (system-on-chip) ASICs using RISC-processor cores to run DSP algorithms. The start-up ...
Electronic Design

Flow Implements C++ DSP Algorithms in FPGAs

Using a design flow put together by Mentor Graphics and Altera, designers can implement complex DSP algorithms in high-performance FPGAs directly from ANSI C++ code. The flow, which is based on Altera ...
Electronic Design

DSP Goes From Algorithm To Implementation

To implement algorithms, digital-signal-processing (DSP) developers have had to rely upon design flows that use manual approaches. Aside from being time consuming, the manual process can invite errors ...
EDN

Conexant upgrades hybrid, DSP algorithms in ADSL chip set

WAYNE, N.J. — Conexant has crafted a new hybrid as well as new DSP algorithms for its ADSL router chip set that allows designers to meet newer DSL Forum bridge tap requirements while enabling ...
Hackaday

Hackaday Prize 2023: Learn DSP With The Portable All-in-One Workstation

Learning Digital Signal Processing (DSP) techniques traditionally involves working through a good bit of mathematics and signal theory. To promote a hands-on approach, [Clyne] developed the DSP PAW ...
Semiconductor Engineering

A DSP For Implementing High-Performance Sensor Fusion On An Embedded Budget

Sensor fusion refers to the combining of data from multiple sensors to obtain more complete and accurate results. By using the information provided by multiple sensing devices, it is possible to ...