TechCrunch

Flow Engineering wants to modernize the hardware engineering design process

Software engineers have a host of tooling to organize their projects, chief being Git software like GitLab or GitHub, but hardware engineers today lack that same organizing principle. They are stuck ...
EDN

Analog design flow certified for UMC’s 22ULP/ULL process

Cadence Design Systems has optimized its analog and mixed-signal IC design flow for UMC’s 22ULP/ULL process technologies targeted at 5G, Internet of Things (IoT), and display applications. The ...
EDN

FPGA synthesis can be a leverage point in your design flow

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA ...
Semiconductor Engineering

Preparing For Test Early In The Design Flow

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...
Design-Reuse

Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node

SANTA ROSA, Calif. April 24, 2024-- Keysight Technologies, Inc. (NYSE: KEYS), Synopsys, Inc. (Nasdaq: SNPS), and Ansys (Nasdaq: ANSS) introduce a new integrated radio frequency (RF) design migration ...
Fast Company

Design Flow: Achieving Breakthrough Creativity And High Yield Production (Part 5)

This seven-part series is a playbook for product leaders. It describes a philosophy of product development and the nitty-gritty process details that bring that philosophy to life. It’s also an ...
Semiconductor Engineering

Tuning Design And Process For High-NA EUV Stitching

Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, ...