Digi Times

IC design houses cautious about placing orders for mature process manufacturing

IC design houses are hesitant to place orders for mature process manufacturing with foundries, due to the still uncertain market outlook for the second half of this year, according to industry sources ...
Nasdaq

Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC’s A16 and N2P Process Technologies

Also announce tool certification for TSMC N3C process and initial collaboration on TSMC’s newest A14 technology SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) today announced it is ...
Digi Times

IC design houses seek lower quotes for mature chipmaking processes

IC design firms are aggressively negotiating with foundry partners to achieve lower quotes for mature process manufacturing in order to alleviate cost pressure, according to industry sources. Except ...
Nasdaq

Ansys Thermal and Multiphysics Solutions Certified for Intel 18A Process and 3D-IC Designs

The qualification process for RedHawk-SC, Totem, and HFSS-IC Pro is currently in progress for the Intel 18A high-performance process node (Intel 18A-P). Customers have the option to request the latest ...
Business Wire

Singapore-based Start-up SiNBLE Launches IC Design Implementation Service

SINGAPORE--(BUSINESS WIRE)--Singapore-based start-up SiNBLE announced its official launch today, offering the integrated circuit (IC) and subsystem design implementation service. This service ...
Semiconductor Engineering

Tackling Reliability In Early IC Design

As the semiconductor industry continues its relentless march towards smaller process nodes and more complex integrated circuits (ICs), the challenge of ensuring reliability has become increasingly ...
Digital News Asia

Penang launches shared lab for IC design validation, onboards second batch of tech collaborators

PSD@5KM+ expands ecosystem with co-working and talent development; 2nd batch of tech collaborators onboarded to expand IC ...
Business Wire

TSMC and Cadence Collaborate to Deliver AI-Driven Advanced-Node Design Flows, Silicon-Proven IP and 3D-IC Solutions

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven ...
EDN

IC verification tool addresses design complexity, productivity gap

A new software combines connectivity, scalability and data-driven artificial intelligence (AI) capabilities to push the boundaries of the IC verification process and make chip design teams more ...
Semiconductor Engineering

Let’s Do The (IC Design) Time Warp Again

For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or ...
Seeking Alpha

Siemens leverages AI to close industry's IC verification productivity gap in new Questa One smart verification solution

Questa One redefines integrated circuit (IC) verification from a reactive process into an intelligent, self-optimizing system Integrated AI-powered automation, predictive analytics and seamless ...
EDN

The future of IC design verification

The complexity of DRC rules increases with shrinking geometries. It is not that the laws of physics change with shrinking IC feature size; they are just more strictly enforced. At one time, there was ...