Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Business Wire

Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group Announces 1.0 Specification

SANTA CLARA, Calif.--(BUSINESS WIRE)--To further the adoption of NAND flash memory technology in the PC platform for an enhanced user experience, the Non-Volatile Memory Host Controller Interface ...
Design-Reuse

Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2

The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard. It is ...
Design-Reuse

Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions

Choosing the right type of memory is critical to ensure that the power and performance requirements are met for the target application. Memory technologies have significantly evolved over the last ...
Electronic Design

UMI Scales the Memory Wall in the Chiplet/Multi-Die Era

What are the current challenges involved with incorporating sufficient HBM into multi-die design? How a new interconnect technology can address the performance, size, and power issues that could ...