While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the ...