EDN

Quad performance serial peripheral interface

Master/Slave with not only single and dual but most of all quad SPI Bus support, is the newest IP Core introduced by Digital Core Design. The DQSPI system is flexible enough to interface directly with ...
EDN

Implementing SPI Master and Slave Functionality

This application note demonstrates a method of implementing the Serial Peripheral Interface (SPI) Master and Slave functionality on Z8 Encore! microcontrollers. The software implementation controls ...
Design-Reuse

APB SPI (Serial Peripheral Interface) master and slave

The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S ...
Design-Reuse

eSPI - DESPI - Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s

The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specificatio ...
Electronic Design

Isolate Your High-Speed SPI Bus Despite Long Propagation Delays

The serial peripheral interface (SPI) bus is a synchronous, full-duplex, serial data link commonly used for the short-distance data exchange between a master device, such as a microcontroller unit ...