The introduction of high-density ASICs and multimillion-gate FPGAs has brought with it a new class of signal integrity problems, both on-chip and off. On-chip parasitic extraction and interconnect ...

As every engineer learns at an early stage, clock edges must be obeyed. In the digital domain, synchronization through global and local clock trees, slew rate and rising/falling times all combine to ...

In today’s ever-shrinking IC package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle.

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most ...

Improves PCIe design productivity using a smarter and streamlined workflow with simulation-driven virtual compliance test solutions Supports design exploration and report generation that speeds ...

Analyzing high speed datacom interfaces is an important task and ensures signal integrity. One major challenge of this analysis is the connection between the physical interface and the oscilloscope, ...

At process technologies of 0.13 µm and smaller, achieving timing closure for system-on-a-chip (SoC) designs becomes a slippery goal. Ever-tinier interconnects are packed closer together, yielding ...

Sunnyvale, Calif. - November 3, 2003 - Virtual Silicon, Inc., a leader in semiconductor intellectual property (SIP), today announced the introduction of a comprehensive set of signal integrity (SI) ...