In today’s ever-shrinking IC package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle.

As every engineer learns at an early stage, clock edges must be obeyed. In the digital domain, synchronization through global and local clock trees, slew rate and rising/falling times all combine to ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs ...

The “Special Report—Test Applications” in our January issue focuses on the software tools as well as logic analyzers, protocol analyzers, BERTs, phase-noise testers, spectrum analyzers, vector network ...

As a signal travels across a network, it focuses only on what it sees in its path. And increases in data rates over the past few decades have made this path a bit more clouded. System infrastructure ...