Test compression offers the benefits of higher quality and lower test cost, but how do you choose the best methodology and tools for your current and future designs? Test compression evaluations ...

Handling timing exception paths in ATPG tools while creating at-speed patterns has always been a tough and tricky task. It is well understood that at-speed testing is a requirement for modern ...

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...

Both launch-off-shift (LOS) and broadside-transition-pattern techniques are finding use in the at-speed test of devices fabricated in 130-nm processes and below. The broadside-transition-pattern ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test ...