With complexity of sub-90nm SOCs driving the need for test to be integrated throughout the design process, both of EDA’s largest vendors today introduced major upgrades to their respective offerings.

The variety of different test methodologies combined with today�s mixture of memory devices creates a complex test profile. The manufacturing test floor hums with activity; a range of memory devices ...

Heterogeneous integration is driving innovation in the semiconductor industry, but it also introduces more complexity in chip design, which translates to more intricate test requirements. The ...

The first generation of serial standard applications is already well established, and the move to the second and third generation is underway, says Randy White, high-speed serial-applications ...

Passive Entry Passive Start (PEPS) technology has become standard in the automotive market for keyless operation. A secure wireless communication system, PEPS enables you to lock and unlock the ...

Among the first decisions to be made when initiating a composites testing program is the selection of test methods to follow. Unless performing highly customized testing, it’s usually not difficult to ...

TOKYO, Sept. 23, 2020 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) has announced its next-generation V93000 testers targeted at advanced digital ...

Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...

There is only so much information we can cram into our “How We Tested” sidebars. In these sidebars that run with every Clear Choice Test article we print, we describe what platform and network ...