When reviewing the agenda of our upcoming Verification Summit here in San Jose this Thursday, the question came to mind of who can actually execute the required complex verification tasks. Can they ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Have you ever released a design, even though you were not fully confident that it was completely verified? Well, you are not alone. The pressure of getting to market faster often results in the ...

With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...